This disclosure relates to integrated circuit devices. More specifically, it relates to a method and structure to create interconnect structures in semiconductor devices with silicon carbide or silicon nitride insulators.
As the dimensions of modern integrated circuitry in semiconductor chips continue to shrink, conventional semiconductor manufacturing technologies are increasingly challenged to make smaller and smaller structures.
In conventional interconnects which use dielectrics such as silicon dioxide to insulate the conductor layers, a barrier or liner layer is often used to separate the conductor material, e.g., copper, from the dielectric. The barrier layers are used to prevent diffusion of the conductor into the dielectric. There are challenges with this approach. The liner layer takes part of the cross-section of the space allotted to the conductor. As the liner layer typically has poorer conductivity, this can be undesirable. Also, the use of a liner introduces two additional interfaces, i.e. between the dielectric and the liner and between the liner and the copper (Cu), which increases the chances of delamination and other adhesion problems.
There exist some dielectrics such as silicon carbide (SiC) and silicon nitride (SiN) which do not require a liner layer, since the conductor does not diffuse into these dielectrics. Although no liner or barrier layer is required for SiC and SiN insulators for Cu interconnects, planarization processes, such as chemical mechanical polishing (CMP) which are commonly used to define the interconnect structure is very challenging. For example, forming Cu interconnects in a Damascene type of structure using a CMP process creates recesses and severe dishing at the Cu interconnect.
Thus, it is desirable to provide processes which can be used to make improved interconnect structures for integrated circuitry using SiC or SiN insulators.